Renesas RL78 Series User Manual

RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT
R01UH0368EJ0210 Rev.2.10 473
Dec 10, 2015
6.5.2 Start timing of counter
Timer count register mn (TCRmn) becomes enabled to operation by setting of TSmn bit of timer channel start register m
(TSm).
Operations from count operation enabled state to timer count Register mn (TCRmn) count start is shown in Table 6-6.
Table 6-6. Operations from Count Operation Enabled State to Timer count Register mn (TCRmn) Count Start
Timer operation mode Operation when TSmn = 1 is set
 Interval timer mode
No operation is carried out from start trigger detection (TSmn=1) until count clock
generation.
The first count clock loads the value of the TDRmn register to the TCRmn
register and the subsequent count clock performs count down operation (see
6.5.3 (1) Start timing in interval timer mode).
 Event counter mode
Writing 1 to the TSmn bit loads the value of the TDRmn register to the TCRmn
register.
The subsequent count clock performs count down operation.
The external trigger detection selected by the STSmn2 to STSmn0 bits in the
TMRmn register does not start count operation (see 6.5.3 (2) Start timing in
event counter mode).
 Capture mode
No operation is carried out from start trigger detection until count clock
generation.
The first count clock loads 0000H to the TCRmn register and the subsequent
count clock performs count up operation (see 6.5.3 (3) Start timing in capture
mode).
 One-count mode
The waiting-for-start-trigger state is entered by writing 1 to the TSmn bit while the
timer is stopped (TEmn = 0).
No operation is carried out from start trigger detection until count clock
generation.
The first count clock loads the value of the TDRmn register to the TCRmn
register and the subsequent count clock performs count down operation (see
6.5.3 (4) Start timing in one-count mode).
 Capture & one-count mode
The waiting-for-start-trigger state is entered by writing 1 to the TSmn bit while the
timer is stopped (TEmn = 0).
No operation is carried out from start trigger detection until count clock
generation.
The first count clock loads 0000H to the TCRmn register and the subsequent
count clock performs count up operation (see 6.5.3 (5) Start timing in capture &
one-count mode (when high-level width is measured)).

Renesas RL78 Series Specifications

General

Brand	Renesas
Model	RL78 Series
Category	Computer Hardware
Language	English