Renesas RL78 Series User Manual

RL78/F13, F14 CHAPTER 27 SAFETY FUNCTIONS
R01UH0368EJ0210 Rev.2.10 1581
Dec 10, 2015
27.2 Registers Used by Safety Functions
The safety functions use the following registers:
Register Each Function of Safety Function
 Flash memory CRC control register (CRC0CTL)
 Flash memory CRC operation result register (PGCRCL)
Flash memory CRC operation function
(high-speed CRC)
 CRC input register (CRCIN)
 CRC operation mode control register (CRCMD)
 CRC data register (CRCD)
CRC operation function
(general-purpose CRC)
 Error address store register (ERADR)
 1-bit error detection interrupt enable register (ECCIER)
 Bit error detection register (ECCER)
 ECC test protect register (ECCTPR)
 ECC test mode register (ECCTMDR)
 Write data inversion register (ECCDWRVR)
RAM-ECC function
 SPM control register (SPMCTRL)
 SP overflow address setting register (SPOFR)
 SP underflow setting register (SPUFR)
Stack pointer monitor function
 Invalid memory access detection control register (IAWCTL) RAM guard function
SFR guard function
Invalid memory access detection function
 Timer input select register 0 (TIS0)
 System clock control register (CKC)
Frequency detection function
 A/D test register (ADTES)
 Analog input channel specification register (ADS)
A/D test function
 Port mode select register (PMS) Digital output signal level detection function for I/O ports
The content of each register is described in 27.3 Operation of Safety Functions.

Renesas RL78 Series Specifications

General

Core	RL78
CPU Clock Speed	Up to 32 MHz
Flash Memory	Up to 512 KB
RAM	Up to 32 KB
Operating Voltage	1.6 V to 5.5 V
Low Power Modes	HALT, STOP, SNOOZE
CPU Architecture	16-bit
Temperature Range	-40°C to +85°C
Package	LQFP
Timers	16-bit timers
Communication Interfaces	UART, I2C, LIN
A/D Converter	12-bit