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Renesas RL78 Series User Manual

Renesas RL78 Series
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RL78/F13, F14 CHAPTER 27 SAFETY FUNCTIONS
R01UH0368EJ0210 Rev.2.10 1590
Dec 10, 2015
27.3.3 RAM-ECC function
The RL78/F13 and RL78/F14 have the RAM-ECC function. This function is used to detect erroneous data (bit errors),
generate interrupt requests, and retain the addresses of bit errors. If only one bit is in error, the data are corrected.
Caution The RAM-ECC function is disabled during on-chip debugging. Therefore, do not use the ECC test mode
to check the on-chip debugging operation. Even if the ECC test mode is used, bit errors are not
detected, error addresses are not stored, or an interrupt is not generated. In addition, even if the bit
error is 1 bit, the data is not corrected.
<Control register>
Register Name Description Access Size
ERADR Error address store register 16 bits
ECCIER
1-bit error detection interrupt enable
register
8 bits
ECCER Bit error detection register 8 bits
ECCTPR ECC test protect register 8 bits
ECCTMDR ECC test mode register 8 bits
ECCDWRVR Write data inversion register 16 bits

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Renesas RL78 Series Specifications

General IconGeneral
CoreRL78
CPU Clock SpeedUp to 32 MHz
Flash MemoryUp to 512 KB
RAMUp to 32 KB
Operating Voltage1.6 V to 5.5 V
Low Power ModesHALT, STOP, SNOOZE
CPU Architecture16-bit
Temperature Range-40°C to +85°C
PackageLQFP
Timers16-bit timers
Communication InterfacesUART, I2C, LIN
A/D Converter12-bit

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