Renesas RL78 Series - Cani Transmit;Receive FIFO Control Register Kh (Cfcchk) (I = 0) (K = 0)

RL78/F13, F14 CHAPTER 18 CAN INTERFACE (RS-CAN LITE)
R01UH0368EJ0210 Rev.2.10 1340
Dec 10, 2015
18.3.46 CANi Transmit/Receive FIFO Control Register kH (CFCCHk) (i = 0) (k = 0)
Address CFCCH0L: F0352H, CFCCH0H: F0353H
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
CFITT[7:0] — — CFTML[1:0] CF
ITR
CF
ITSS
CFM[1:0]
After
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit Symbol Bit Name Description R/W
15 to 8 CFITT[7:0] Message Transmission Interval
Configuration
Set a message transmission interval.
Set these bits to a value within a range of H'00 to H'FF.
R/W
7, 6 — Reserved These bits are always read as 0. The write value should
always be 0.
R
5, 4 CFTML[1:0] Transmit Buffer Link Configuration Set the transmit buffer number to be linked to the
transmit/receive FIFO buffer.
R/W
3 CFITR Transmit/Receive FIFO Interval
Timer Resolution
0: Clock obtained by frequency-dividing fCLK/2 by the
ITRCP[15:0] value
1: Clock obtained by frequency-dividing f
CLK/2 by the
ITRCP[15:0] value × 10
R/W
2 CFITSS Interval Timer Clock Source Select 0: Clock selected by the CFITR bit
1: CANi bit time clock
R/W
1, 0 CFM[1:0] Transmit/Receive FIFO Mode Select
b1 b0
0 0 : Receive mode
0 1 : Transmit mode
1 0 : Setting prohibited
1 1 : Setting prohibited
R/W
• CFITT[7:0] Bits
These bits are used to set a message transmission interval when transmitting messages continuously from a
transmit/receive FIFO buffer whose CFM[1:0] bits are set to B'01 (transmit mode).
Clear the CFE bit to 0 (no transmit/receive FIFO buffer is used) and then modify the CFITT[7:0] bits.
• CFTML[1:0] Bits
These bits are used to set the number of transmit buffer to be linked to the transmit/receive FIFO buffer when
the CFM[1:0] bits are set to B'01 (transmit mode).
Setting the CFDC[2:0] bits to B'001 or more enables the setting of the CFTML[1:0] bits.
Modify these bits only in global reset mode.
• CFITR Bit
This bit is valid when the setting of the CFITSS bit is 0.
Setting this bit to 0 selects the clock obtained by frequency-dividing f
CLK/2 by the ITRCP[15:0] value.
Setting this bit to 1 selects the clock obtained by frequency-dividing f
CLK/2 by the ITRCP[15:0] value × 10.
Modify the CFITR bit with the CFE bit in theCFCCLk register set to 0 (no transmit/receive FIFO buffer is used).
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