Renesas RL78 Series User Manual

RL78/F13, F14 CHAPTER 18 CAN INTERFACE (RS-CAN LITE)
R01UH0368EJ0210 Rev.2.10 1371
Dec 10, 2015
18.3.74 CANi Transmit History Buffer Control Register (THLCCi) (i = 0)
Address THLCC0L: F037CH, THLCC0H: F037DH
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
— — — — — THL
DTE
THL
IM
THL
IE
— — — — — — — THL
E
After
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit Symbol Bit Name Description R/W
15 to 11 — Reserved These bits are always read as 0. The write value should
always be 0.
R
10 THLDTE Transmit History Target Buffer
Select
0: Entry from transmit/receive FIFO buffers
1: Entry from transmit buffers, transmit/receive FIFO
buffers
R/W
9 THLIM Transmit History Interrupt Source
Select
0: When 6 sets of data have been stored in the transmit
history buffer
1: When a single set of transmit history data has been
stored
R/W
8 THLIE Transmit History Interrupt Enable 0: Transmit history interrupt is disabled.
1: Transmit history interrupt is enabled.
R/W
7 to 1 — Reserved These bits are always read as 0. The write value should
always be 0.
R
0 THLE Transmit History Buffer Enable 0: Transmit history buffer is not used.
1: Transmit history buffer is used.
R/W
• THLDTE Bit
When this bit is set to 0, the transmit history data of messages transmitted from transmit/receive FIFO buffers is
stored in the transmit history buffer. When this bit is set to 1, the transmit history data of messages transmitted
from transmit buffers and transmit/receive FIFO buffers is stored in the transmit history buffer.
Modify this bit only in channel reset mode.
• THLIM Bit
This bit is used to select a transmit history interrupt source.
Modify this bit only in channel reset mode.
• THLIE Bit
When the THLIE bit is set to 1 and the source selected by the THLIM bit has occurred, a transmit history
interrupt request is generated. Modify the THLIE bit with the THLE bit set to 0.
• THLE Bit
Setting this bit to 1 makes the transmit history buffer available. When data transmission from the buffer selected
by the THLDTE bit has been completed, the transmit history data of transmit messages is stored in the transmit
history buffer.
Modify this bit only in channel communication mode or channel halt mode.

Renesas RL78 Series Specifications

General

Core	RL78
CPU Clock Speed	Up to 32 MHz
Flash Memory	Up to 512 KB
RAM	Up to 32 KB
Operating Voltage	1.6 V to 5.5 V
Low Power Modes	HALT, STOP, SNOOZE
CPU Architecture	16-bit
Temperature Range	-40°C to +85°C
Package	LQFP
Timers	16-bit timers
Communication Interfaces	UART, I2C, LIN
A/D Converter	12-bit