Renesas RL78 Series User Manual

RL78/F13, F14 CHAPTER 10 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER
R01UH0368EJ0210 Rev.2.10 688
Dec 10, 2015
10.2 Configuration of Clock Output/Buzzer Output Controller
The clock output/buzzer output controller includes the following hardware.
Table 10-1. Configuration of Clock Output/Buzzer Output Controller
Item Configuration
Control registers
Clock output select registers 0 (CKS0)
Port mode register 14 (PM14)
Port register 14 (P14)
10.3 Registers Controlling Clock Output/Buzzer Output Controller
The following registers are used to control the clock output/buzzer output controller.
 Clock output select registers 0 (CKS0)
 Port mode register 14 (PM14)
 Port register 14 (P14)
10.3.1 Clock output select register 0 (CKS0)
These registers set output enable/disable for clock output or for the buzzer frequency output pin (PCLBUZ0), and
set the output clock.
Select the clock to be output from the PCLBUZ0 pin by using the CKS0 register.
The CKS0 register are set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.

Renesas RL78 Series Specifications

General

Core	RL78
CPU Clock Speed	Up to 32 MHz
Flash Memory	Up to 512 KB
RAM	Up to 32 KB
Operating Voltage	1.6 V to 5.5 V
Low Power Modes	HALT, STOP, SNOOZE
CPU Architecture	16-bit
Temperature Range	-40°C to +85°C
Package	LQFP
Timers	16-bit timers
Communication Interfaces	UART, I2C, LIN
A/D Converter	12-bit