Renesas RL78 Series User Manual

RL78/F13, F14 CHAPTER 18 CAN INTERFACE (RS-CAN LITE)
R01UH0368EJ0210 Rev.2.10 1408
Dec 10, 2015
18.10.5 Buffer Setting
Set sizes and interrupt sources of buffers. For transmit/receive FIFO buffers that are set to transmit mode, set transmit
buffers to be linked.
Figure 18-20 shows the buffer configuration. Figure 18-21 shows the buffer setting procedure.
Figure 18-20. Buffer Configuration
Maximum 16 buffers
4 buffers fixed
Caution Receive buffers, receive FIFO buffers, transmit/receive FIFO buffer, and transmit buffers are located in succession.
Remark n = 0 to 15
Receive buffers
Receive buffer 0
Receive buffer n
Receive FIFO 0
Receive FIFO 1
Transmit/receive FIFO 0
Transmit buffer 0
Receive FIFO buffers
Transmit/receive FIFO buffer
Transmit buffers
Transmit buffer 3

Renesas RL78 Series Specifications

General

Core	RL78
CPU Clock Speed	Up to 32 MHz
Flash Memory	Up to 512 KB
RAM	Up to 32 KB
Operating Voltage	1.6 V to 5.5 V
Low Power Modes	HALT, STOP, SNOOZE
CPU Architecture	16-bit
Temperature Range	-40°C to +85°C
Package	LQFP
Timers	16-bit timers
Communication Interfaces	UART, I2C, LIN
A/D Converter	12-bit