Renesas RL78 Series User Manual

RL78/F13, F14 CHAPTER 18 CAN INTERFACE (RS-CAN LITE)
R01UH0368EJ0210 Rev.2.10 1369
Dec 10, 2015
18.3.72 CANi Transmit Buffer Register pDL (TMDF2p) (i = 0) (p = 0 to 3)
Address TMDF20L: F060CH, TMDF20H: F060DH TMDF21L: F061CH, TMDF21H: F061DH
TMDF22L: F062CH, TMDF22H: F062DH TMDF23L: F063CH, TMDF23H: F063DH
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
TMDB5[7:0] TMDB4[7:0]
After Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit Symbol Bit Name Description R/W
15 to 8 TMDB5[7:0] Transmit Buffer Data Byte 5 Set transmit buffer data. R/W
7 to 0 TMDB4[7:0] Transmit Buffer Data Byte 4 R/W
Modify this register when the TMTRM bit in the corresponding TMSTSp register is set to 0 (no transmit request is
present). If this register is linked to any transmit/receive FIFO buffer, do not write data to this register.
This register can be read/written when the RPAGE bit in the GRWCR register is 1.

Renesas RL78 Series Specifications

General

Core	RL78
CPU Clock Speed	Up to 32 MHz
Flash Memory	Up to 512 KB
RAM	Up to 32 KB
Operating Voltage	1.6 V to 5.5 V
Low Power Modes	HALT, STOP, SNOOZE
CPU Architecture	16-bit
Temperature Range	-40°C to +85°C
Package	LQFP
Timers	16-bit timers
Communication Interfaces	UART, I2C, LIN
A/D Converter	12-bit