Renesas RL78 Series User Manual

RL78/F13, F14 CHAPTER 30 FLASH MEMORY
R01UH0368EJ0210 Rev.2.10 1647
Dec 10, 2015
30.8.3 Procedure for accessing data flash memory
The data flash memory is stopped after a reset is released. To access the data flash memory, initial settings must be
specified as described below.
After the initial settings are specified, the data flash memory can be read by CPU instructions and can be read or rewritten
by using a data flash library.
<1> Set 1 to bit 0 (DFLEN) of the data flash control register (DFLCTL).
<2> Use a software timer to wait for the setup to finish.
Setup time: 5
 s
<3> After the wait, the data flash memory can be accessed.
Cautions 1. Accessing the data flash memory is prohibited during the setup time.
2. Transition to the STOP mode is not possible during the setup time. To enter the STOP mode during
the setup time, clear DFLEN to 0 and then execute the STOP instruction.
3. The high-speed on-chip oscillator should be kept operating during data flash rewrite. If it is kept
stopping, the high-speed on-chip oscillator clock should be operated (HIOSTOP = 0). The data flash
library should be executed after 30
 s have elapsed.

Renesas RL78 Series Specifications

General

Core	RL78
CPU Clock Speed	Up to 32 MHz
Flash Memory	Up to 512 KB
RAM	Up to 32 KB
Operating Voltage	1.6 V to 5.5 V
Low Power Modes	HALT, STOP, SNOOZE
CPU Architecture	16-bit
Temperature Range	-40°C to +85°C
Package	LQFP
Timers	16-bit timers
Communication Interfaces	UART, I2C, LIN
A/D Converter	12-bit