RL78/F13, F14 CHAPTER 18 CAN INTERFACE (RS-CAN LITE)
R01UH0368EJ0210 Rev.2.10 1301
Dec 10, 2015
18.3.10 CAN Global Configuration Register H (GCFGH)
Address GCFGHL: F0324H, GCFGHH: F0325H
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
ITRCP[15:0]
After Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit Symbol Bit Name Description R/W
15-0 ITRCP[15:0] Interval Timer Prescaler Set If the set value is M, fCLK/2 is frequency-divided by M.
Setting H'0000 is prohibited, when the interval timer
is in use.
R/W
Modify the GCFGH register only in global reset mode.
• ITRCP[15:0] Bits
These bits are used to set a clock source division value of the interval timer for FIFO buffers. For details, see
18.6.3 (1) Interval Transmission Function.
To Next Page
Loading...
