Name: Renesas RL78 Series
Brand: Renesas
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RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT

R01UH0368EJ0210 Rev.2.10 459

Dec 10, 2015

6.3.13 Timer output level register m (TOLm)

The TOLm register is a register that controls the timer output level of each channel.

The setting of the inverted output of channel n by this register is reflected at the timing of set or reset of the timer output

signal while the timer output is enabled (TOEmn = 1) in the Slave channel output mode (TOMmn = 1). In the master channel

output mode (TOMmn = 0), this register setting is invalid.

The TOLm register can be set by a 16-bit memory manipulation instruction.

Set the lower 8 bits of the TOLm register with an 8-bit memory manipulation instruction with TOLmL.

Reset signal generation clears this register to 0000H.

Figure 6-23. Format of Timer Output Level Register m (TOLm)

Address: F01BCH, F01BDH (TOL0), F01FCH, F01FDH (TOL1) After reset: 0000H R/W

Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

TOLm 0 0 0 0 0 0 0 0

TOL

Control of timer output level of channel n

0 Non-inverted output (active-high)

1 Inverted output (active-low)

Caution Be sure to clear bits 15 to 8 and 0 to “0”. (unit 1, 0: Group E products, unit 0: Group A products)

Be sure to clear bits 15 to 8 and 0 of unit 0 and bits 15 to 4 and 0 of unit 1 to "0". (Group B, C, and D

products)

Remarks 1. If the value of this register is rewritten during timer operation, the timer output logic is inverted when the

timer output signal changes next, instead of immediately after the register value is rewritten.

2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)

3. TOL1n is not provided in the Group A products.

TOL17 to TOL14 are not provided in the Group B, C, and D products.

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