RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT
R01UH0368EJ0210 Rev.2.10 874
Dec 10, 2015
15.5.5 Slave reception
Slave reception is an operation wherein this MCU receives data from another device in the state of a transfer clock being
input from another device.
3-Wire Serial I/O CSI00 CSI01 CSI10 CSI11
Target channel Channel 0 of SAU0 Channel 1 of SAU0 Channel 0 of SAU1 Channel 1 of SAU1
Pins used SCK00, SI00 SCK01, SI01 SCK10, SI10 SCK11, SI11
Interrupt INTCSI00 INTCSI01 INTCSI10 INTCSI11
Transfer end interrupt only (Setting the buffer empty interrupt is prohibited.)
Error detection flag Overrun error detection flag (OVFmn) only
Transfer data length 7 to 16 bits
Transfer rate Max. fMCK/6 [Hz]
Notes 1, 2
Data phase Selectable by the DAPmn bit of the SCRmn register
• DAPmn = 0: Data input starts from the start of the serial clock operation.
• DAPmn = 1: Data input starts half a clock before the start of the serial clock operation.
Clock phase Selectable by the CKPmn bit of the SCRmn register
• CKPmn = 0: Forward
• CKPmn = 1: Reverse
Data direction MSB or LSB first
Notes 1. Because the external serial clock input to the SCK00, SCK01, SCK10, and SCK11 pins is sampled internally
and used, the fastest transfer rate is f
MCK/6 [Hz].
2. Use this operation within a range that satisfies the conditions above and the AC characteristics in the
electrical specifications.
Remarks 1. f
MCK: Operation clock frequency of target channel
2. m: Unit number (m = 0, 1), n: Channel number (n = 0, 1), mn = 00, 01, 10, 11
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