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Renesas RL78 Series User Manual

Renesas RL78 Series
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RL78/F13, F14 CHAPTER 19 DTC
R01UH0368EJ0210 Rev.2.10 1432
Dec 10, 2015
19.2.3 DTC Vector Table
When the DTC is activated, one control data is selected according to the data read from the vector table which has been
assigned to each activation source, and the selected control data is read from the DTC control data area.
Table 19-5 lists the DTC activation sources and DTC vector addresses. A one byte of the DTC vector table is assigned
to each activation source, and the lower 8 bits for the start address of the DTC control data are stored in each area to select
one of the 24 sets. The higher 8 bits for the DTC vector address are set by the DTCBAR register, and 00H to 2DH are
allocated to the lower 8 bits corresponding to the DTC activation source.
Caution
Change the start address of the DTC control data area to be set in the vector table when the corresponding bit
among bits DTCENi0 to DTCENi7 (i = 0 to 5
Note
) in the DTCENi register is set to 0 (DTC activation disabled).
Note Products of groups A, B, C, and D: i = 0 to 4
Products of group E: i = 0 to 5

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Renesas RL78 Series Specifications

General IconGeneral
CoreRL78
CPU Clock SpeedUp to 32 MHz
Flash MemoryUp to 512 KB
RAMUp to 32 KB
Operating Voltage1.6 V to 5.5 V
Low Power ModesHALT, STOP, SNOOZE
CPU Architecture16-bit
Temperature Range-40°C to +85°C
PackageLQFP
Timers16-bit timers
Communication InterfacesUART, I2C, LIN
A/D Converter12-bit

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