Renesas RL78 Series User Manual

RL78/F13, F14 CHAPTER 11 WATCHDOG TIMER
R01UH0368EJ0210 Rev.2.10 693
Dec 10, 2015
CHAPTER 11 WATCHDOG TIMER
11.1 Functions of Watchdog Timer
The watchdog timer operates on the WDT-dedicated low-speed on-chip oscillator clock (f
WDT).
The watchdog timer is used to detect an inadvertent program loop. If a program loop is detected, an internal reset signal
is generated.
Program loop is detected in the following cases.
 If the watchdog timer counter overflows
 If a 1-bit manipulation instruction is executed on the watchdog timer enable register (WDTE)
 If data other than “ACH” is written to the WDTE register
 If data is written to the WDTE register during a window close period
When a reset occurs due to the watchdog timer, bit 4 (WDCLRF) of the reset control flag register (RESF) is set to 1. For
details of the RESF register, see CHAPTER 24 RESET FUNCTION.
When 75% of the overflow time + 1/2 f
WDT is reached, an interval interrupt can be generated.

Renesas RL78 Series Specifications

General

Core	RL78
CPU Clock Speed	Up to 32 MHz
Flash Memory	Up to 512 KB
RAM	Up to 32 KB
Operating Voltage	1.6 V to 5.5 V
Low Power Modes	HALT, STOP, SNOOZE
CPU Architecture	16-bit
Temperature Range	-40°C to +85°C
Package	LQFP
Timers	16-bit timers
Communication Interfaces	UART, I2C, LIN
A/D Converter	12-bit