RL78/F13, F14 CHAPTER 17 LIN/UART MODULE (RLIN3)
R01UH0368EJ0210 Rev.2.10 1245
Dec 10, 2015
17.6.1 Change to LIN Self-Test Mode
LIN self-test mode is entered by writing to the LSTCn register.
The transition to LIN self-test mode can be confirmed when the LSTM bit in the LSTCn register becomes 1.
When changing to LIN self-test mode, be sure to execute a specific sequence. In that sequence, information must be written
three times consecutively to the LIN self-test control register, as follows:
Change to LIN reset mode
Set the OM0 bit in the LCUCn register to 0 (LIN reset mode).
Read the OMM0 bit in the LMSTn register; verify that it is 0 (LIN reset mode).
Select a LIN mode
LMD bits in LMDn register = 00b (LIN master mode) or 11b (LIN slave mode [fixed baud rate])
1st write: LSTCn register = 1010 0111b (A7H)
2nd write: LSTCn register = 0101 1000b (58H)
3rd write: LSTCn register = 0000 0001b (01H)
Verify the transition to LIN self-test mode
Read the LSTM bit in the LSTCn register; verify that it is 1 (LIN self-test mode).
If the key of the first write (A7H) is written twice by mistake, the transition to LIN self-test mode is canceled. The above
sequence should be retried from the step of first write. In addition, if a write to another LIN-related register is performed
during transition to LIN self-test mode (three consecutive write operations to the LSTCn register), the transition is also
canceled.
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