Renesas RL78 Series - Timer RD Output Master Enable Register 1 (TRDOER1)

RL78/F13, F14 CHAPTER 8 TIMER RD
R01UH0368EJ0210 Rev.2.10 578
Dec 10, 2015
8.2.8 Timer RD Output Master Enable Register 1 (TRDOER1)
Figure 8-9. Format of Timer RD Output Master Enable Register 1 (TRDOER1)
[Output Compare Function, PWM Function, Reset Synchronous PWM Mode,
Complementary PWM Mode, and PWM3 Mode]
Address: F0267H After Reset: FFH
Note 1
Symbol 7 6 5 4 3 2 1 0
TRDOER1 ED1
EC1 EB1 EA1 ED0
EC0 EB0 EA0
ED1
TRDIOD1 output disable
Note 2
R/W
0 Output enabled R/W
1 Output disabled (TRDIOD1 pin functions as an I/O port.)
EC1
TRDIOC1 output disable
Note 2
R/W
0 Output enabled R/W
1 Output disabled (TRDIOC1 pin functions as an I/O port.)
EB1
TRDIOB1 output disable
Note 2
R/W
0 Output enabled R/W
1 Output disabled (TRDIOB1 pin functions as an I/O port.)
EA1
TRDIOA1 output disable
Notes 2, 3
R/W
0 Output enabled R/W
1 Output disabled (TRDIOA1 pin functions as an I/O port)
ED0
TRDIOD0 output disable
Note 2
R/W
0 Output enabled R/W
1 Output disabled (TRDIOD0 pin functions as an I/O port.)
EC0
TRDIOC0 output disable
Note 2
R/W
0 Output enabled R/W
1 Output disabled (TRDIOC0 pin functions as an I/O port.)
EB0 TRDIOB0 output disable R/W
0 Output enabled R/W
1 Output disabled (TRDIOB0 pin functions as an I/O port.)
EA0
TRDIOA0 output disable
Notes 3, 4
R/W
0 Output enabled R/W
1 Output disabled (TRDIOA0 pin functions as an I/O port)
Notes 1. The value after reset is undefined when FRQSEL4 = 1 in the user option byte (000C2H/020C2H) and
TRD0EN = 0 in the PER1 register. If it is necessary to read the initial value, set fCLK to fIH and TRD0EN =
1 before reading.
2. Set to 1 in PWM3 mode.
3. Set to 1 in PWM function.
4. Set to 1 in reset synchronous PWM mode and complementary PWM mode.