Renesas RL78 Series

RL78/F13, F14 CHAPTER 19 DTC
R01UH0368EJ0210 Rev.2.10 1463
Dec 10, 2015
19.4.7 Number of High-speed DTC Execution Clock Cycles
Table 19-13 lists the operations following high-speed DTC activation and required number of clock cycles for each
operation.
Table 19-13. Operations Following High-speed DTC Activation and Required Number of Cycles
Vector Read
Control Data
Data Read Data Write
Read Write-back
1 1
Note 1
Note 2 Note 2
Notes 1. For the number of clock cycles required for control data write-back, refer to Table 19-14 Number of Clock
Cycles Required for Control Data Write-Back Operation.
2. For the number of clock cycles required for data read/write, refer to Table 19-15 Number of Clock Cycles
Required for Data Read/Write Operation.
Table 19-14. Number of Clock Cycles Required for Control Data Write-Back Operation
HDTCCRm Register Setting Address Setting Control Register to be Written Back Numbe
r
of
Clock
Cycles
HDAMOD
m
HSAMOD
m
HRPTSEL
m
HMODE
m
Source Destination
HDTCCT
m
Register
HDTRLD
m
Register
HDTSAR
m
Register
HDTDAR
m
Register
0 0 X 0 Fixed Fixed Written
back
Not
written
back
Not
written
back
Not
written
back
1
0 1 X 0 Incremente
d
Fixed Written
back
Not
written
back
Written
back
Not
written
back
1
1 0 X 0 Fixed Incremente
d
Written
back
Not
written
back
Not
written
back
Written
back
1
1 1 X 0 Incremente
d
Incremente
d
Written
back
Not
written
back
Written
back
Written
back
1
0 X 1 1 Repeat
area
Fixed Written
back
Not
written
back
Written
back
Not
written
back
1
1 X 1 1 Incremente
d
Written
back
Not
written
back
Written
back
Written
back
1
X 0 0 1 Fixed Repeat
area
Written
back
Not
written
back
Not
written
back
Written
back
1
X 1 0 1 Incremente
d
Written
back
Not
written
back
Written
back
Written
back
1
Remark m = 0, 1; X: 0 or 1