RL78/F13, F14 CHAPTER 18 CAN INTERFACE (RS-CAN LITE)
R01UH0368EJ0210 Rev.2.10 1263
Dec 10, 2015
18.3 Register Descriptions
Table 18-3 lists the registers of the CAN module.
The values after reset of the registers allocated to the CAN RAM area (F03A0H to F0681H) are those after the CAN
RAM is initialized.
Table 18-3. List of CAN Module Registers (1/22)
Address Special Function Register (SFR) Name Symbol R/W Access Size After
Reset
1 bit 8 bits 16 bits
F02C1H Peripheral enable register 2 PER2 R/W √ √ — 00H
F02C2H CAN clock select register CANCKSEL R/W √ √ — 00H
F0300H CAN0 bit configuration register L C0CFGLL C0CFGL R/W — √ √ 0000H
F0301H C0CFGLH — √
F0302H CAN0 bit configuration register H C0CFGHL C0CFGH R/W — √ √ 0000H
F0303H C0CFGHH — √
F0304H CAN0 control register L C0CTRLL C0CTRL R/W — √ √ 0005H
Note
F0305H C0CTRLH — √
F0306H CAN0 control register H C0CTRHL C0CTRH R/W — √ √ 0000H
F0307H C0CTRHH — √
F0308H CAN0 status register L C0STSLL C0STSL R — √ √ 0005H
Note
F0309H C0STSLH — √
F030AH CAN0 status register H C0STSHL C0STSH R — √ √ 0000H
F030BH C0STSHH — √
F030CH CAN0 error flag register L C0ERFLLL C0ERFLL R/W — √ √ 0000H
F030DH C0ERFLLH — √
F030EH CAN0 error flag register H C0ERFLHL C0ERFLH R — √ √ 0000H
F030FH C0ERFLHH — √
F0322H CAN global configuration register L GCFGLL GCFGL R/W — √ √ 0000H
F0323H GCFGLH — √
F0324H CAN global configuration register H GCFGHL GCFGH R/W — √ √ 0000H
F0325H GCFGHH — √
F0326H CAN global control register L GCTRLL GCTRL R/W — √ √ 0005H
Note
F0327H GCTRLH — √
F0328H CAN global control register H GCTRHL GCTRH R/W — √ √ 0000H
F0329H GCTRHH — √
F032AH CAN global status register GSTSL GSTS R — √ √ 000DH
Note
F032BH GSTSH — √
F032CH CAN global error flag register GERFLL R/W — √ — 00H
F032EH CAN timestamp register GTSC R — — √ 0000H
F032FH — —
F0330H CAN receive rule number configuration
register
GAFLCFGL GAFLCFG R/W — √ √ 0000H
F0331H GAFLCFGH — √
F0332H CAN receive buffer number configuration
register
RMNBL RMNB R/W — √ √ 0000H
F0333H — — —
F0334H CAN receive buffer receive complete flag
register
RMND0L RMND0 R/W — √ √ 0000H
F0335H RMND0H — √
F0338H CAN receive FIFO control register 0 RFCC0L RFCC0 R/W — √ √ 0000H
F0339H RFCC0H — √
F033AH CAN receive FIFO control register 1 RFCC1L RFCC1 R/W — √ √ 0000H
F033BH RFCC1H — √
Note When the CAN0EN bit in the PER2 register is set to 0, the read value is undefined.
When the CAN0EN bit in the PER2 register is set to 1, the read value is the initial value listed above.
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