RL78/F13, F14 CHAPTER 5 CLOCK GENERATOR
R01UH0368EJ0210 Rev.2.10 422
Dec 10, 2015
5.6.9 Conditions Before Clock Oscillation Is Stopped
The following lists the register flag settings for stopping the clock oscillation (disabling external clock input) and
conditions before the clock oscillation is stopped.
Table 5-9. Conditions Before the Clock Oscillation Is Stopped and Flag Settings
Clock
Conditions Before Clock Oscillation Is Stopped
(External Clock Input Disabled)
Flag Settings of SFR
Register
High-speed on-chip oscillator clock MCS = 1 or CLS = 1
(The CPU is operating on a clock other than the high-
speed on-chip oscillator clock.)
HIOSTOP = 1
X1 clock MCS = 0 or CLS = 1
(The CPU is operating on a clock other than the high-
speed system clock.)
MSTOP = 1
External main system clock
PLL clock SELPLLS = 0
(The CPU is operating on a clock other than the PLL
clock.)
PLLON = 0
XT1 clock CLS = 0
(The CPU is operating on a clock other than the
subsystem/low-speed on-chip oscillator clock.)
XTSTOP = 1
External subsystem clock
Low-speed on-chip oscillator clock CLS = 0
(The CPU is operating on a clock other than the
subsystem/low-speed on-chip oscillator clock.)
SELLOSC = 0 and
WUTMMCK0 = 0
Remark MCS: Bit 5 of the system clock control register (CKC)
CLS: Bit 7 of the system clock control register (CKC)
HIOSTOP: Bit 0 of the clock operation status control register (CSC)
XTSTOP: Bit 6 of the clock operation status control register (CSC)
MSTOP: Bit 7 of the clock operation status control register (CSC)
SELPLLS: Bit 3 of the PLL status register (PLLSTS)
PLLON: Bit 0 of the PLL control register (PLLCTL)
SELLOSC: Bit 1 of the clock select register (CKSEL)
WUTMMCK0: Bit 4 of the operation speed mode control register (OSMC)
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