Renesas RL78 Series

RL78/F13, F14 CHAPTER 5 CLOCK GENERATOR
R01UH0368EJ0210 Rev.2.10 421
Dec 10, 2015
Table 5-6. Maximum Time Required for Type 2 (2)
Note 1
Set Value Before Switchover Set Value After Switchover
MCM0 MCM0
0
(f
MAIN = fIH)
1
(fMAIN = fMX)
0
(f
MAIN = fIH)
6 f
IH/fMX clock
1
(f
MAIN = fMX)
3 clocks
Note 1. For fIH  32 MHz
Table 5-7. Maximum Time Required for Type 3
Set Value Before Switchover Set Value After Switchover
CSS CSS
0
(f
CLK = fMP)
1
(fCLK = fSL)
0
(f
CLK = fMP)
1 + 2 f
MP/fSL clock
1
(f
CLK = fSL)
3 clocks
Table 5-8. Maximum Time Required for Type 4
Set Value Before Switchover Set Value After Switchover
SELPLL SELPLL
0
(f
MP = fMAIN)
1
(fMP = fPLL)
0
(f
MP = fMAIN)
2 clocks
1
(f
MP = fPLL)
2 f
PLL/fMAIN clock
Remarks 1. The number of clocks listed in Tables 5-5 to 5-8 is the number of CPU clocks before switchover.
2. Calculate the number of clocks in Tables 5-5 to 5-8 by removing the decimal portion.
Example When switching the main system clock from the high-speed on-chip oscillator clock (with
16 MHz) to the high-speed system clock
(@ oscillation with f
IH = 16 MHz, fMX = 10 MHz)
3 f
IH/fMX = 3  1.6 = 4.8 5 clocks