Renesas RL78 Series User Manual

RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT
R01UH0368EJ0210 Rev.2.10 461
Dec 10, 2015
6.3.15 Noise filter enable registers 1, 2 (NFEN1, NFEN2)
The NFEN1, NFEN2 registers is used to set whether the noise filter can be used for the timer input signal to each channel.
Enable the noise filter by setting the corresponding bits to 1 on the pins in need of noise removal.
When the noise filter is ON, match detection and synchronization of the 2 clocks is performed with the CPU/peripheral
hardware clock (f
MCK). When the noise filter is OFF, only synchronization is performed with the CPU/peripheral hardware
clock (f
MCK)
Note
.
Set the NFEN1 and NFEN2 registers by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Note For details, see 6.5.1 (2) When valid edge of input signal via the TImn pin is selected (CCSmn = 1) and 6.5.2
Start timing of counter.

Renesas RL78 Series Specifications

General

Core	RL78
CPU Clock Speed	Up to 32 MHz
Flash Memory	Up to 512 KB
RAM	Up to 32 KB
Operating Voltage	1.6 V to 5.5 V
Low Power Modes	HALT, STOP, SNOOZE
CPU Architecture	16-bit
Temperature Range	-40°C to +85°C
Package	LQFP
Timers	16-bit timers
Communication Interfaces	UART, I2C, LIN
A/D Converter	12-bit