Renesas RL78 Series User Manual

RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT
R01UH0368EJ0210 Rev.2.10 462
Dec 10, 2015
Figure 6-25. Format of Noise Filter Enable Register 1 (NFEN1) (1/2)
Address: F0071H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
NFEN1 TNFEN07 TNFEN06 TNFEN05 TNFEN04 TNFEN03 TNFEN02 TNFEN01 TNFEN00
TNFEN07 Enable/disable using noise filter of TI07 pin input signal
0 Noise filter OFF
1 Noise filter ON
TNFEN06 Enable/disable using noise filter of TI06 pin input signal
0 Noise filter OFF
1 Noise filter ON
TNFEN05 Enable/disable using noise filter of TI05 pin input signal
0 Noise filter OFF
1 Noise filter ON
TNFEN04 Enable/disable using noise filter of TI04 pin input signal
0 Noise filter OFF
1 Noise filter ON
TNFEN03 Enable/disable using noise filter of TI03 pin input signal
0 Noise filter OFF
1 Noise filter ON
TNFEN02 Enable/disable using noise filter of TI02 pin input signal
0 Noise filter OFF
1 Noise filter ON
TNFEN01 Enable/disable using noise filter of TI01 pin input signal
0 Noise filter OFF
1 Noise filter ON
TNFEN00 Enable/disable using noise filter of TI00 pin input signal
0 Noise filter OFF
1 Noise filter ON
Caution The pin to be used can be changed by setting the TIS17 and TIS16 bits in the timer input select
register 1 (TIS1).
When TIS17, TIS16 = 0, 0: The use of the noise filter of the TI07 pin can be enabled or disabled.
When TIS17, TIS16 = 1, 0: The use of the noise filter of the RxD0 pin can be enabled or disabled.
Remark The presence or absence of timer I/O pins of channel 0 to 7 depends on the product. See Table 6-2 Timer
I/O Pins provided in Each Product for details.

Renesas RL78 Series Specifications

General

Core	RL78
CPU Clock Speed	Up to 32 MHz
Flash Memory	Up to 512 KB
RAM	Up to 32 KB
Operating Voltage	1.6 V to 5.5 V
Low Power Modes	HALT, STOP, SNOOZE
CPU Architecture	16-bit
Temperature Range	-40°C to +85°C
Package	LQFP
Timers	16-bit timers
Communication Interfaces	UART, I2C, LIN
A/D Converter	12-bit