RL78/F13, F14 CHAPTER 12 A/D CONVERTER
R01UH0368EJ0210 Rev.2.10 756
Dec 10, 2015
12.8.2 If no interrupt is generated after A/D conversion ends
If the A/D conversion result value is outside the range of values specified by the A/D conversion result comparison
function (which is set up by using the ADRCK bit and ADUL/ADLL register), the A/D conversion end interrupt request
signal (INTAD) is not generated.
ï‚· While in the select mode
If the A/D conversion end interrupt request signal (INTAD) is not generated after A/D conversion ends, the clock
request signal (an internal signal) is automatically set to the low level, and supplying the high-speed on-chip oscillator
clock stops. If a hardware trigger is input later, A/D conversion work is again performed in the SNOOZE mode.
ï‚· While in the scan mode
If the A/D conversion end interrupt request signal (INTAD) is not generated even once during A/D conversion of the
four channels, the clock request signal (an internal signal) is automatically set to the low level after A/D conversion
of the four channels ends, and supplying the high-speed on-chip oscillator clock stops. If a hardware trigger is input
later, A/D conversion work is again performed in the SNOOZE mode.
Figure 12-41. Operation Example When No Interrupt Is Generated After A/D Conversion Ends (While in Scan
Mode)
ADCS
Interrupt signal
(INTAD)
INTRTC
Clock request signal
(internal signal)
Conversion
channels
Channel 1 Channel 2 Channel 3 Channel 4
No interrupt is generated when
conversion ends for any channel.
The clock request signal
is set to the low level.
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