Renesas RL78 Series - Timer RD Mode Register (TRDMR)

RL78/F13, F14 CHAPTER 8 TIMER RD
R01UH0368EJ0210 Rev.2.10 574
Dec 10, 2015
8.2.5 Timer RD Mode Register (TRDMR)
Figure 8-6. Format of Timer RD Mode Register (TRDMR)
Address: F0264H After Reset:00H
Note 1
Symbol <7> <6> <5> <4> 3 2 1 <0>
TRDMR TRDBFD1 TRDBFC1 TRDBFD0 TRDBFC0 0 0 0 TRDSYNC
TRDBFD1
TRDGRD1 register function select
Note 2
R/W
0 General register R/W
1 Buffer register for TRDGRB1 register
TRDBFC1
TRDGRC1 register function select
Note 2
R/W
0 General register R/W
1 Buffer register for TRDGRA1 register
TRDBFD0
TRDGRD0 register function select
Note 2
R/W
0 General register R/W
1 Buffer register for TRDGRB0 register
TRDBFC0
TRDGRC0 register function select
Notes 2, 3
R/W
0 General register R/W
1 Buffer register for TRDGRA0 register
TRDSYNC
Timer RD synchronous
Note 4
R/W
0
TRD0 and TRD1 operate independently
R/W
1 TRD0 and TRD1 operate synchronously
Notes 1. The value after reset is undefined when FRQSEL4 = 1 in the user option byte (000C2H/020C2H) and
TRD0EN = 0 in the PER1 register. If it is necessary to read the initial value, set f
CLK to fIH and TRD0EN =
1 before reading.
2. In the output compare function, if 0 (TRDGRji register output pin is changed) is selected for the IOj3 (j =
C or D) bit in the TRDIORCi (i = 0 or 1) register, set the TRDBFji bit in the TRDMR register to 0.
3. Set to 0 (general register) in complementary PWM mode.
4. Set to 0 (TRD0 and TRD1 operate independently) in reset synchronous PWM mode, complementary
PWM mode, and PWM3 mode.
Bits 3 to1 Nothing is assigned R/W
—
The write value must be 0. The read value is 0.
R