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RL78/F13, F14 CHAPTER 17 LIN/UART MODULE (RLIN3)

R01UH0368EJ0210 Rev.2.10 1211

Dec 10, 2015

17.4.3 Transmission/Reception Data Buffering

This section explains the buffer processing that takes place when the LIN/UART module sends or receives data

continuously.

(1) Transmission of LIN Frames

For an 8-byte transmission, the contents stored in registers LDBn1 to LDBn8 are sequentially transmitted to data areas 1

to 8 of the LIN frame. In the case of a 4-byte transmission, the contents stored in registers LDBn1 to LDBn4 are

transmitted to data areas 1 to 4 of the LIN frame, but the contents of registers LDBn5 to LDBn8 are not transmitted. The

transmitted checksum data is stored in the LCBRn register.

Figure 17-16 depicts the LIN transmission processing and the required buffer.

Figure 17-16. LIN Transmission Processing and Required Buffer

(a) Frame Separate Mode

Setting the FSM bit in the LDFCn register to 1 turns on the frame separate mode.

In frame separate mode, a header and a response are transmitted when prompted by separate transmission

start requests.

When the transmission of a header is finished, the HTRC flag in the LSTn register turns 1 (successful header

transmission).

Use frame separate mode when sending or receiving response data of 9 bytes or greater in LIN master mode.

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