RL78/F13, F14 CHAPTER 25 POWER-ON-RESET CIRCUIT
R01UH0368EJ0210 Rev.2.10 1559
Dec 10, 2015
25.4 Cautions for Power-on-reset Circuit
In a system where the supply voltage (V
DD) fluctuates for a certain period in the vicinity of the POR detection voltage
(V
POR, VPDR), the system may be repeatedly reset and released from the reset status. In this case, the time from release of
reset to the start of the operation of the microcontroller can be arbitrarily set by taking the following action.
<Action>
After releasing the reset signal, wait for the supply voltage fluctuation period of each system by means of a software
counter that uses a timer, and then initialize the ports.
Figure 25-3. Example of Software Processing After Reset Release (1/2)
(1) If supply voltage fluctuation is 50 ms or less in vicinity of POR detection voltage
Notes 1. If reset is generated again during this period, initialization processing <2> is not started.
2. A flowchart is shown on the next page.
Remark m = 0, 1, n = 0 to 7
; Check the reset source, etc.
Note 2
Note 1
Reset
Initialization
processing <1>
50 ms has passed?
(TMIFmn = 1?)
Initialization
processing <2>
Setting timer array unit
(to measure 50 ms)
; Initial setting for port.
Setting of division ratio of system clock,
such as setting of timer or A/D converter.
Ye s
No
Power-on-reset
Clearing WDT
; f
CLK = High-speed on-chip oscillator clock (4 MHz)
Source: f
MCK (4 MHz) /2
7
,
where comparison value = 789: Approx. 50 ms
Timer starts (TS0n = 1).
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