Renesas RL78 Series - DTC Control Register J (Dtccrj) (J = 0 to 23)

RL78/F13, F14 CHAPTER 19 DTC
R01UH0368EJ0210 Rev.2.10 1441
Dec 10, 2015
19.2.7 DTC Control Register j (DTCCRj) (j = 0 to 23)
The DTCCRj register is used to control the DTC operating mode.
Figure 19-7. Format of DTC Control Register j (DTCCRj)
Address: Refer to 19.2.2 DTC Control Data Allocation. After reset: Undefined
Symbol 7 6 5 4 3 2 1 0
DTCCRj 0 SZ RPTINT CHNE DAMOD SAMOD RPTSEL MODE
Bit 7 Reserved R/W
0 Set to 0. R/W
SZ Data size selection R/W
0 8 bits R/W
1 16 bits
RPTINT Enabling/disabling repeat mode interrupts R/W
0 Interrupt generation disabled R/W
1 Interrupt generation enabled
The setting of the RPTINT bit is invalid when the MODE bit is 0 (normal mode).
CHNE Enabling/disabling chain transfers
R/W
0 Chain transfers disabled
R/W
1 Chain transfers enabled
Set the CHNE bit in the DTCCR23 register to 0 (chain transfers disabled).
DAMOD Transfer destination address control
R/W
0 Fixed
R/W
1 Incremented
The setting of the DAMOD bit is invalid when the MODE bit is 1 (repeat mode) and the RPTSEL bit
is 0 (transfer destination is the repeat area).
SAMOD Transfer source address control
R/W
0 Fixed
R/W
1 Incremented
The setting of the SAMOD bit is invalid when the MODE bit is 1 (repeat mode) and the RPTSEL bit
is 1 (transfer source is the repeat area).
RPTSEL Repeat area selection
R/W
0 Transfer destination is the repeat area
R/W
1 Transfer source is the repeat area
The setting of the RPTSEL bit is invalid when the MODE bit is 0 (normal mode).
MODE Transfer mode selection R/W
0 Normal mode R/W
1 Repeat mode
Caution Do not access the DTCCRj register using a DTC transfer.