Renesas RL78 Series User Manual

RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE
R01UH0368EJ0210 Rev.2.10 192
Dec 10, 2015
3.4.7 Based addressing
[Function]
Based addressing uses the contents of a register pair specified with the instruction word or 16-bit immediate data as
a base address, and 8-bit immediate data or 16-bit immediate data as offset data. The sum of these values is used to
specify the target address.
[Operand format]
Identifier Description

[HL + byte], [DE + byte], [SP + byte] (only the space from F0000H to FFFFFH is specifiable)

word[B], word[C] (only the space from F0000H to FFFFFH is specifiable)

word[BC] (only the space from F0000H to FFFFFH is specifiable)

ES:[HL + byte], ES:[DE + byte] (higher 4-bit addresses are specified by the ES register)

ES:word[B], ES:word[C] (higher 4-bit addresses are specified by the ES register)

ES:word[BC] (higher 4-bit addresses are specified by the ES register)
Figure 3-55. Example of [SP+byte]
FFFFFH
F0000H
SP
Target memory
Memory
Offset
Stack area
Specifies a
stack area
Instruction code
<1>
<1>
byte <2>
<2>
SP (stack pointer) <1> indicates the stack as the
target.
By indicating an offset from the address (top of the
stack) currently pointed to by the stack pointer,
“byte” <2> indicates the target memory (SP + byte).

Renesas RL78 Series Specifications

General

Core	RL78
CPU Clock Speed	Up to 32 MHz
Flash Memory	Up to 512 KB
RAM	Up to 32 KB
Operating Voltage	1.6 V to 5.5 V
Low Power Modes	HALT, STOP, SNOOZE
CPU Architecture	16-bit
Temperature Range	-40°C to +85°C
Package	LQFP
Timers	16-bit timers
Communication Interfaces	UART, I2C, LIN
A/D Converter	12-bit