Renesas RL78 Series User Manual

RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE
R01UH0368EJ0210 Rev.2.10 193
Dec 10, 2015
Figure 3-56. Example of [HL + byte], [DE + byte]
Figure 3-57. Example of word[B], word[C]
FFFFFH
F0000H
rp(HL/DE)
[HL + byte], [DE + byte]
Target
array
of data
Offset
Address of
an array
Other data in
the array
Target memory
Memory
Instruction code
OP-code
byte
<1> <2>
<2>
<1>
<2>
<1> <2>
Either pair of registers <1> specifies the address
where the target array of data starts in the 64-Kbyte
area from F0000H to FFFFFH.
“byte” <2> specifies an offset within the array to
the target location in memory.
F0000H
r(B/C)
FFFFFH
word [B], word [C]
OP-code
Low Addr.
High Addr.
Instruction code
Array of
word-sized
data
“word” <1> specifies the address where the target
array of word-sized data starts in the 64-Kbyte area
from F0000H to FFFFFH.
Either register <2> specifies an offset within the
array to the target location in memory.
Target memory
Memory
<1>
<1> <2> <1> <2>
<2>
<2>
Address of a word
within an array
Offset

Renesas RL78 Series Specifications

General

Core	RL78
CPU Clock Speed	Up to 32 MHz
Flash Memory	Up to 512 KB
RAM	Up to 32 KB
Operating Voltage	1.6 V to 5.5 V
Low Power Modes	HALT, STOP, SNOOZE
CPU Architecture	16-bit
Temperature Range	-40°C to +85°C
Package	LQFP
Timers	16-bit timers
Communication Interfaces	UART, I2C, LIN
A/D Converter	12-bit