Renesas RL78 Series User Manual

RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE
R01UH0368EJ0210 Rev.2.10 194
Dec 10, 2015
Figure 3-58. Example of word[BC]
Figure 3-59. Example of ES:[HL + byte], ES:[DE + byte]
FFFFFH
F0000H
rp(BC)
word [BC]
OP-code
Low Addr.
High Addr.
Instruction code
Address of a word
within an array
Offset
Array of
word-sized
data
“word” <1> specifies the address where the target
array of word-sized data starts in the 64-Kbyte area
from F0000H to FFFFFH.
A pair of registers <2> specifies an offset within
the array to the target location in memory.
Target memory
Memory
<1>
<1>
<1> <2>
<2>
<2>
XFFFFH
X0000H
rp(HL/DE)
X0000H
ES
ES: [HL + byte], ES: [DE + byte]
Target
array
of data
Address of
an array
OP-code
byte
<3>
Specifies a
64-Kbyte area
Offset
<3>
<1>
Instruction code
<1> <2> <3> <3><1>
<1>
<2>
<2>
<2>
Target memory
Memory
Other data in
the array
The ES register <1> specifies a 64-Kbyte
area within the overall 1-Mbyte space as
the four higher-order bits, X, of the address range.
Either pair of registers <2> specifies the address
where the target array of data starts in the 64-Kbyte
area specified in the ES register <1>.
“byte” <3> specifies an offset within the array to the
target location in memory.

Renesas RL78 Series Specifications

General

Brand	Renesas
Model	RL78 Series
Category	Computer Hardware
Language	English