Renesas RL78 Series - Page 495

RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT
R01UH0368EJ0210 Rev.2.10 463
Dec 10, 2015
Figure 6-25. Format of Noise Filter Enable Register 2 (NFEN2) (2/2)
Address: F0072H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
NFEN2 TNFEN17 TNFEN16 TNFEN15 TNFEN14 TNFEN13 TNFEN12 TNFEN11 TNFEN10
TNFEN17 Enable/disable using noise filter of TI17 pin input signal
0 Noise filter OFF
1 Noise filter ON
TNFEN16 Enable/disable using noise filter of TI16 pin input signal
0 Noise filter OFF
1 Noise filter ON
TNFEN15 Enable/disable using noise filter of TI15 pin input signal
0 Noise filter OFF
1 Noise filter ON
TNFEN14 Enable/disable using noise filter of TI14 pin input signal
0 Noise filter OFF
1 Noise filter ON
TNFEN13 Enable/disable using noise filter of TI13 pin input signal
0 Noise filter OFF
1 Noise filter ON
TNFEN12 Enable/disable using noise filter of TI12 pin input signal
0 Noise filter OFF
1 Noise filter ON
TNFEN11 Enable/disable using noise filter of TI11 pin input signal
0 Noise filter OFF
1 Noise filter ON
TNFEN10 Enable/disable using noise filter of TI00 pin input signal
0 Noise filter OFF
1 Noise filter ON
Remarks 1. The presence or absence of timer I/O pins of channel 0 to 7 depends on the product. See Table 6-2 Timer
I/O Pins provided in Each Product for details.
2. NFEN2 is not provided in the Group A products.
Bits 7 to 4 are not provided in the Group B, C, and D products.