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Renesas RL78 Series - Page 1373

Renesas RL78 Series
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RL78/F13, F14 CHAPTER 18 CAN INTERFACE (RS-CAN LITE)
R01UH0368EJ0210 Rev.2.10 1341
Dec 10, 2015
CFITSS Bit
Setting this bit to 0 selects the clock selected by the CFITR bit as the clock source for counting by the interval
timer.
Setting this bit to 1 selects the CANi bit time clock as the clock source for counting by the interval timer. Clear
the CFE bit to 0 (no transmit/receive FIFO buffer is used) before modifying the CFITSS bit.
CFM[1:0] Bits
These bits are used to select transmit/receive FIFO mode. Modify these bits only in global reset mode.

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