Renesas RL78 Series User Manual

RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT
R01UH0368EJ0210 Rev.2.10 1011
Dec 10, 2015
Figure 15-154. Flowchart of Stop Condition Generation
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0, 1), mn = 00, 01, 10, 11
Starting generation of stop condition.
End of IIC communication
Writing 0 to the SOEmn bit
Writing 1 to the SOmn bit
Writing 1 to the CKOmn bit
Writing 0 to the SOmn bit
Completion of data
transmission/data reception
Wait
Secure a wait time so that the specifications of
I
2
C on the slave side are satisfied.
Operation is stopped

Renesas RL78 Series Specifications

General

Core	RL78
CPU Clock Speed	Up to 32 MHz
Flash Memory	Up to 512 KB
RAM	Up to 32 KB
Operating Voltage	1.6 V to 5.5 V
Low Power Modes	HALT, STOP, SNOOZE
CPU Architecture	16-bit
Temperature Range	-40°C to +85°C
Package	LQFP
Timers	16-bit timers
Communication Interfaces	UART, I2C, LIN
A/D Converter	12-bit