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Renesas RL78 Series User Manual

Renesas RL78 Series
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RL78/F13, F14 CHAPTER 16 SERIAL INTERFACE IICA
R01UH0368EJ0210 Rev.2.10 1031
Dec 10, 2015
Figure 16-8. Format of IICA Flag Register 0 (IICF0)
Note Bits 6 and 7 are read-only.
Cautions 1. Write to the STCEN bit only when the operation is stopped (IICE0 = 0).
2. As the bus release status (IICBSY0 = 0) is recognized regardless of the actual bus status
when STCEN0 = 1, when generating the first start condition (STT0 = 1), it is necessary to
verify that no third party communications are in progress in order to prevent such
communications from being destroyed.
3. Write to IICRSV0 only when the operation is stopped (IICE0 = 0).
Remark STT0: Bit 1 of IICA control register 00 (IICCTL00)
IICE0: Bit 7 of IICA control register 00 (IICCTL00)
<7>
STCF0
Condition for clearing (STCF0 = 0)
• Cleared by STT0 = 1
• When IICE0 = 0 (operation stop)
• Reset
Condition for setting (STCF0 = 1)
• Generating start condition unsuccessful and the
STT0 bit cleared to 0 when communication
reservation is disabled (IICRSV0 = 1).
STCF0
0
1
Generate start condition
Start condition generation unsuccessful: clear the STT0 flag
STT0 clear flag
IICF0
Symbol
<6>
IICBSY0
5
0
4
0
3
0
2
0
<1>
STCEN0
<0>
IICRSV0
Address: FFF52H After reset: 00H R/W
Note
Condition for clearing (IICBSY0 = 0)
• Detection of stop condition
• When IICE0 = 0 (operation stop)
• Reset
Condition for setting (IICBSY0 = 1)
• Detection of start condition
• Setting of the IICE0 bit when STCEN0 = 0
IICBSY0
0
1
Bus release status (communication initial status when STCEN0 = 1)
Bus communication status (communication initial status when STCEN0 = 0)
I
2
C bus status flag
Condition for clearing (STCEN0 = 0)
• Cleared by instruction
• Detection of start condition
• Reset
Condition for setting (STCEN0 = 1)
• Set by instruction
STCEN0
0
1
After operation is enabled (IICE0 = 1), enable generation of a start condition upon detection of
a stop condition.
After operation is enabled (IICE0 = 1), enable generation of a start condition without detecting
a stop condition.
Initial start enable trigger
Condition for clearing (IICRSV0 = 0)
• Cleared by instruction
• Reset
Condition for setting (IICRSV0 = 1)
• Set by instruction
IICRSV0
0
1
Enable communication reservation
Disable communication reservation
Communication reservation function disable bit

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Renesas RL78 Series Specifications

General IconGeneral
BrandRenesas
ModelRL78 Series
CategoryComputer Hardware
LanguageEnglish

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