Renesas RL78 Series - Page 1126

RL78/F13, F14 CHAPTER 16 SERIAL INTERFACE IICA
R01UH0368EJ0210 Rev.2.10 1094
Dec 10, 2015
Figure 16-32. Example of Master to Slave Communication
(When 9-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (4/4)
(4) Data ~ restart condition ~ address
L
H
L
H
L
H
IICA0
STT0
(ST trigger)
SPT0
(SP trigger)
ACKD0
(ACK detection)
WTIM0
(8 or 9 clock wait)
ACKE0
(ACK control)
MSTS0
(communication status)
TRC0
(transmit/receive)
SCLA0 (bus)
(clock line)
WREL0
(wait cancellation)
INTIICA0
(interrupt)
SDAA0 (bus)
(data line)
AD6
IICA0
STD0
(ST detection)
SPD0
(SP detection)
ACKD0
(ACK detection)
WTIM0
(8 or 9 clock wait)
ACKE0
(ACK control)
MSTS0
(communication status)
TRC0
(transmit/receive)
WREL0
(wait cancellation)
INTIICA0
(interrupt)
Master side
Bus line
Slave side
Slave address
D 1 3
ACK
<i>
L
H
H
L
H
Restart condition
D 1 2 D 1 1 D 1 0
AD5 AD4 AD3 AD2 AD1
<ii>
<iii>
<7>
<8>
Note 2
Note 1
: Wait state by master device
: Wait state by slave device
: Wait state by master and slave devices
Notes 1. Make sure that the time between the rise of the SCLA0 pin signal and the generation of the start condition
after a restart condition has been issued is at least 4.7  s when specifying standard mode and at least
0.6
 s when specifying fast mode.
2. For releasing wait state during reception of a slave device, write “FFH” to IICA0 or set the WREL0 bit.