Renesas RL78 Series - Page 1152

RL78/F13, F14 CHAPTER 17 LIN/UART MODULE (RLIN3)
R01UH0368EJ0210 Rev.2.10 1120
Dec 10, 2015
(12) LIN/UART Space Configuration Register (LSCn)
Address: F06CAH
7 6 5 4 3 2 1 0
— — IBS[1:0] —
IBSH[2:0]
Value after reset:
0 0 0 0 0 0 0 0
Bit Symbol Bit Name Function R/W
2 to 0 IBSH[2:0] Inter-Byte Space (Header)/
Response Space Select
b2 b0
0 0 0: 0 Tbit
0 0 1: 1 Tbit
0 1 0: 2 Tbits
0 1 1: 3 Tbits
1 0 0: 4 Tbits
1 0 1: 5 Tbits
1 1 0: 6 Tbits
1 1 1: 7 Tbits
R/W
3 — Reserved This bit is always read as 0. The write value should always be
0.
R/W
5, 4 IBS[1:0] Inter-Byte Space Select
b5 b4
0 0: 0 Tbit
0 1: 1 Tbit
1 0: 2 Tbits
1 1: 3 Tbits
R/W
7, 6 — Reserved These bits are always read as 0. The write value should always
be 0.
R/W
Set the LSCn register when the OMM0 bit in the LMSTn register is 0 (LIN reset mode).
Some combinations of the set values result in the length of a frame or a response exceeding the timeout time. Set the
appropriate values in this register.
IBSH[2:0] bits (inter-byte space (header)/response space select bits)
The IBSH bits set the width of the inter-byte space (header) of the transmission frame header field and the response space.
0 Tbit to 7 Tbits can be set.
The response space setting is enabled only during response transmission; setting is disabled during response reception.
The inter-byte space (header) is equal to the response space.
IBS[1:0] bits (inter-byte space select bits)
The IBS bits set the width of the inter-byte space of the transmission frame response field.
0 Tbit to 3 Tbits can be set.
These bits are enabled only during response transmission; these are disabled during response reception.