RL78/F13, F14 CHAPTER 17 LIN/UART MODULE (RLIN3)
R01UH0368EJ0210 Rev.2.10 1132
Dec 10, 2015
(21) LIN/UART Data Field Configuration Register (LDFCn)
Address: F06D4H
7 6 5 4 3 2 1 0
LSS FSM CSM RFT RFDL[3:0]
Value after reset:
0 0 0 0 0 0 0 0
Bit Symbol Bit Name Function R/W
3 to 0 RFDL[3:0] Response Field Length Select
b3 b0
0 0 0 0: 0 byte (+ checksum)
0 0 0 1: 1 byte (+ checksum)
0 0 1 0: 2 bytes (+ checksum)
:
0 1 1 1: 7 bytes (+ checksum)
1 0 0 0: 8 bytes (+ checksum)
Settings other than the above are prohibited.
R/W
4 RFT Response Field Communication Direction
Select
0: Reception
1: Transmission
R/W
5 CSM Checksum Select 0: Classic checksum mode
1: Enhanced checksum mode
R/W
6 FSM Frame Separate Mode Select 0: Frame separate mode is not set.
1: Frame separate mode is set.
R/W
7 LSS Transmission/Reception Continuation
Select
0: The data group to be transmitted/received next is the
last one.
1: The data group to be transmitted/received next is not
the last one. (Checksum is not included.)
R/W
RFDL[3:0] bits (response field length select bits)
The RFDL bits set the length of the response field data.
The data length can be 0 to 8 bytes excluding the checksum size.
To transmit response data with the FSM bit set to 0 (not frame separate mode), set the RFDL bits before header transmission
(the FTS bit in the LTRCn register is 0).
To transmit response data with the FSM bit set to 1 (frame separate mode), set the RFDL bits before response transmission
(the RTS bit in the LTRCn register is 0).
To receive response data, set the RFDL bits before header transmission (the FTS bit in the LTRCn register is 0).
When response data of 9 bytes or more is to be transmitted or received, set the RFDL bits before data group
transmission/reception (RTS bit in the LTRCn register is 0).
During communication of response data of 9 bytes or more, only the last data group (the LSS bit is 0) includes the checksum,
and no other groups (the LSS bit is 1) include the checksum.
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