Renesas RL78 Series User Manual

RL78/F13, F14 CHAPTER 17 LIN/UART MODULE (RLIN3)
R01UH0368EJ0210 Rev.2.10 1220
Dec 10, 2015
(b) Target Time Area for LIN Error Detection
Figure 17-20 shows the time domain in which the LIN/UART module in master mode performs monitoring for
error detection.
Figure 17-20. Target Time Area for LIN Error Detection (LIN Master Mode)
<Wake-up transmission>
Wake-up
Bit error
Data 1 Data 2 Data 8 Checksum
Header Response
Frame
Sync field
ID field
Bit error
In transmission only
In reception only
<Frame transmission/reception>
Frame timeout error
Only in transmission
of break field and
break delimiter
Break field
Response timeout error
Only stop bit in reception
Physical bus
error
Response
preparation error
Checksum error
Physical bus error
Only in reception
with enhance
checksum mode
selected
Framing error

Renesas RL78 Series Specifications

General

Core	RL78
CPU Clock Speed	Up to 32 MHz
Flash Memory	Up to 512 KB
RAM	Up to 32 KB
Operating Voltage	1.6 V to 5.5 V
Low Power Modes	HALT, STOP, SNOOZE
CPU Architecture	16-bit
Temperature Range	-40°C to +85°C
Package	LQFP
Timers	16-bit timers
Communication Interfaces	UART, I2C, LIN
A/D Converter	12-bit