Renesas RL78 Series User Manual

RL78/F13, F14 CHAPTER 17 LIN/UART MODULE (RLIN3)
R01UH0368EJ0210 Rev.2.10 1257
Dec 10, 2015
Figure 17-46. Determination of Received Data when Noise Filter is Used
LRXDn
Start
bit
Bit
1
Bit
2
Bit
3
Bit
4
Bit
5
Bit
6
Bit
7
Stop
bit
Start bit
Bit
0
[Determination of the received data when using noise filter]
[Determination of the received data at the time of the noise filter unused]
(n = 0, 1)
Synchronization LRXDn
Prescaler clock
Prescaler clock
Sampling clock
Sampling point
Noise filtering
FF1 signal of circuit
Noise filtering
FF2 signal of circuit
Start bit
Noise filter output
Start bit
Start bit
Start bit
Noise filter output
Start bit
Prescaler clock
Sampling clock
Sampling point
Synchronization LRXDn
Start bit

Renesas RL78 Series Specifications

General

Core	RL78
CPU Clock Speed	Up to 32 MHz
Flash Memory	Up to 512 KB
RAM	Up to 32 KB
Operating Voltage	1.6 V to 5.5 V
Low Power Modes	HALT, STOP, SNOOZE
CPU Architecture	16-bit
Temperature Range	-40°C to +85°C
Package	LQFP
Timers	16-bit timers
Communication Interfaces	UART, I2C, LIN
A/D Converter	12-bit