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Renesas RL78 Series - Page 1329

Renesas RL78 Series
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RL78/F13, F14 CHAPTER 18 CAN INTERFACE (RS-CAN LITE)
R01UH0368EJ0210 Rev.2.10 1297
Dec 10, 2015
BORF Flag
This flag is set to 1 when 11 consecutive recessive bits have been detected 128 times and the CAN module
returns from the bus off state. However, this flag is not set to 1 if the CAN module returns from the bus off state
in either of the following ways before 11 consecutive recessive bits are detected 128 times.
The CHMDC[1:0] bits in the CiCTRL register are set to B'01 (channel reset mode).
The RTBO bit in the CiCTRL register is set to 1 (forcible return from the bus off state is made).
The BOM[1:0] bits in the CiCTRH register are set to B'01 (transition to channel halt mode at bus off entry).
The CHMDC[1:0] bits in the CiCTRL register are set to B'10 (channel halt mode) before 11 consecutive
recessive bits are detected 128 times with the BOM[1:0] bits set to B'11 (transition to channel halt mode upon
a request from the program during bus off).
BOEF Flag
This flag is set to 1 when the state becomes bus off state (TEC[7:0] value > 255). This flag is also set to 1 when
the state becomes bus off state with the BOM[1:0] bits in the CiCTRH register set to B'01 (transition to channel
halt mode at bus off entry).
EPF Flag
This flag becomes 1 when the CAN module becomes error passive state (REC[7:0] or TEC[7:0] value > 127).
This flag becomes 1 only when the REC[7:0] or TEC[7:0] value exceeds 127 for the first time. Therefore, if the
program writes 0 to this flag with the REC[7:0] or TEC[7:0] value remaining over 127, this bit is not set to 1 until
both REC [7:0] and TEC[7:0] values become 127 or less and then the REC[7:0] or TEC[7:0] value exceeds 127
again.
EWF Flag
This flag is set to 1 only when the REC[7:0] or TEC[7:0] value exceeds 95 for the first time. Therefore, if the
program writes 0 to this flag with the REC[7:0] or TEC[7:0] value remaining over 95, this bit is not set to 1 until
both REC [7:0] and TEC[7:0] values become 95 or less and then the REC[7:0] or TEC[7:0] value exceeds 95
again.
BEF Flag
This flag is set to 1 when any one of the ADERR, B0ERR, B1ERR, CERR, AERR, FERR, and SERR flags in the
CiERFLL register is set to 1.

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