RL78/F13, F14 CHAPTER 18 CAN INTERFACE (RS-CAN LITE)
R01UH0368EJ0210 Rev.2.10 1326
Dec 10, 2015
• RFIE Bit
Setting the RFIE bit to 1 enables receive FIFO interrupts. Modify this bit when the RFE bit is set to 0 (no receive
FIFO buffer is used).
• RFE Bit
Setting the RFE bit to 1 makes receive FIFO buffers available. Clearing this bit to 0 sets the RFEMP flag in the
RFSTSm register to 1 (the receive FIFO buffer contains no unread message (buffer empty)). Modify this bit only
in global operating mode or global test mode.
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