Renesas RL78 Series - Page 14

Index-8
7.5.5 Procedure for Setting Pins TRJO0 and TRJIO0 ............................................................................. 565
7.5.6 When Timer RJ is not Used ............................................................................................................ 565
7.5.7 When Timer RJ Operating Clock is Stopped .................................................................................. 565
7.5.8 Procedure for Setting STOP Mode (Event Counter Mode) ............................................................. 565
7.5.9 Functional Restriction in STOP Mode (Event Counter Mode Only) ................................................ 566
7.5.10 When Count is Forcibly Stopped by TSTOP Bit ........................................................................... 566
7.5.11 Digital Filter .................................................................................................................................. 566
7.5.12 When Selecting fIL as Count Source ............................................................................................ 566
CHAPTER 8 TIMER RD ........................................................................................................................ 567
8.1 Overview ...................................................................................................................................... 567
8.2 Registers ..................................................................................................................................... 569
8.2.1 Peripheral enable register 1 (PER1) ............................................................................................... 570
8.2.2 Clock Select Register (CKSEL) ...................................................................................................... 571
8.2.3 Timer RD ELC Register (TRDELC) ................................................................................................ 572
8.2.4 Timer RD Start Register (TRDSTR) ............................................................................................... 573
8.2.5 Timer RD Mode Register (TRDMR) ............................................................................................... 574
8.2.6 Timer RD PWM Function Select Register (TRDPMR) .................................................................... 575
8.2.7 Timer RD Function Control Register (TRDFCR) ............................................................................ 576
8.2.8 Timer RD Output Master Enable Register 1 (TRDOER1) .............................................................. 578
8.2.9 Timer RD Output Master Enable Register 2 (TRDOER2) .............................................................. 579
8.2.10 Timer RD Output Control Register (TRDOCR) ............................................................................. 580
8.2.11 Timer RD Digital Filter Function Select Register i (TRDDFi) (i = 0 or 1) ....................................... 583
8.2.12 Timer RD Control Register i (TRDCRi) (i = 0 or 1) ....................................................................... 585
8.2.13 Timer RD I/O Control Register Ai (TRDIORAi) (i = 0 or 1) ............................................................ 590
8.2.14 Timer RD I/O Control Register Ci (TRDIORCi) (i = 0 or 1) ........................................................... 592
8.2.15 Timer RD Status Register i (TRDSRi) (i = 0 or 1) ......................................................................... 594
8.2.16 Timer RD Interrupt Enable Register i (TRDIERi) (i = 0 or 1) ......................................................... 598
8.2.17 Timer RD PWM Function Output Level Control Register i (TRDPOCRi) (i = 0 or 1) ..................... 599
8.2.18 Timer RD Counter i (TRDi) (i = 0 or 1) .......................................................................................... 600
8.2.19 Timer RD General Registers Ai, Bi, Ci, and Di (TRDGRAi, TRDGRBi,TRDGRCi, TRDGRDi)
(i = 0 or 1) ..................................................................................................................................... 602
8.2.20 PWM Output Delay Control Register 0 (PWMDLY0) .................................................................... 611
8.2.21 Port mode registers (PM1, PM3, PM12) ....................................................................................... 612
8.3 Operation ..................................................................................................................................... 613
8.3.1 Items Common to Multiple Modes .................................................................................................. 613
8.3.2 Input Capture Function ................................................................................................................... 624
8.3.3 Output Compare Function .............................................................................................................. 628
8.3.4 PWM Function ................................................................................................................................ 633
8.3.5 Reset Synchronous PWM Mode .................................................................................................... 637
8.3.6 Complementary PWM Mode .......................................................................................................... 640