RL78/F13, F14 CHAPTER 21 INTERRUPT FUNCTIONS
R01UH0368EJ0210 Rev.2.10 1500
Dec 10, 2015
5. Even if the RPTINT bit in the DTCCRj register (j = 0 to 23) is set to 0 (disabling the interrupt while
the DTC module is in repeat mode), when the comparator detection 0 interrupt source is
generated, the INTFLG06 bit is set to 1. For details, see (A) Internal maskable interrupt (only
comparator detection 0 interrupt) in Figure 21-1. Basic Configuration of Interrupt Function.
6. If an INTPn interrupt is generated, the bit m in the interrupt source determination flag register 0
(INTFLG0) is set regardless of the settings of the bits in the interrupt mask flag register (MKxx)
and interrupt mask register (INTMSK).
m: Bit number (m = 0, 1, 2, 7), n: INTP interrupt number (n = 4, 5, 8, 13)
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