Renesas RL78 Series User Manual

RL78/F13, F14 CHAPTER 23 STANDBY FUNCTION
R01UH0368EJ0210 Rev.2.10 1524
Dec 10, 2015
Table 23-1. Operating Statuses in HALT Mode (1/2)
HALT Mode Setting
Item
When HALT Instruction Is Executed While CPU Is Operating on Main System Clock
When CPU Is Operating
on High-speed On-chip
Oscillator Clock (f
IH)
When CPU Is
Operating on X1
Clock (fX)
When CPU Is
Operating on
External Main
System Clock
(f
EX)
When CPU Is Operating
on PLL Clock (f
PLL)
System clock Clock supply to the CPU is stopped
Main system clock fIH Operation continues
(cannot be stopped)
Operation disabled Only operation of the
PLL clock continues
(and cannot be stopped).
Clocks other than the
PLL clock do not
operate.
fX Operation disabled Operation continues
(cannot be stopped)
Cannot operate
fEX Cannot operate Operation
continues
(cannot be
stopped)
fPLL Operation disabled Operation
disabled
Operation continues
(cannot be stopped)
Subsystem clock fXT Status before HALT mode was set is retained
fEXS
fIL Set by bit 1 (HPIEN) of on-chip debug option byte (000C3H/020C3H), bit 0 (SELLOSC) of
the CKSEL register, and bit 4 (WUTMMCK0) of the OSMC register.
 WUTMMCK0 = 1: Oscillates
 WUTMMCK0 = 0 and SELLOSC = 1: Oscillates
 WUTMMCK0 = 0, SELLOSC = 0, and HPIEN = 1: Oscillates
 WUTMMCK0 = 0, SELLOSC = 0, and HPIEN = 0: Stops
fWDT Set by bits 0 (WDSTBYON) and 4 (WDTON) of user option byte (000C0H/020C0H)
 WDTON = 0: Stops
 WDTON = 1 and WDSTBYON = 1: Oscillates
 WDTON = 1 and WDSTBYON = 0: Stops
CPU Operation stopped
Code flash memory
Data flash memory
RAM Operation stopped (operation can continue during DTC transfer)
Port (latch) Status before HALT mode was set is retained
Timer array unit Operable
Real-time clock (RTC)
Watchdog timer See CHAPTER 11 WATCHDOG TIMER
Clock monitor Operable (fIL operates)
Timer RJ Operable
Timer RD
Clock output/buzzer output
A/D converter
D/A converter
Comparator
Serial array unit (SAU)
Serial interface (IICA)
DTC
ELC Linking between operational function blocks is possible.
LIN/UART module (RLIN3) Operable
CAN interface (RS-CAN lite)
Power-on-reset function
Voltage detection function
External interrupt

Renesas RL78 Series Specifications

General

Core	RL78
CPU Clock Speed	Up to 32 MHz
Flash Memory	Up to 512 KB
RAM	Up to 32 KB
Operating Voltage	1.6 V to 5.5 V
Low Power Modes	HALT, STOP, SNOOZE
CPU Architecture	16-bit
Temperature Range	-40°C to +85°C
Package	LQFP
Timers	16-bit timers
Communication Interfaces	UART, I2C, LIN
A/D Converter	12-bit