Renesas RL78 Series User Manual

RL78/F13, F14 CHAPTER 24 RESET FUNCTION
R01UH0368EJ0210 Rev.2.10 1551
Dec 10, 2015
Table 24-3. States of Bits in RESF/LVIM/LVIS Registers When Reset Requests are Generated
Reset Source
Register
RESET Input Reset by
POR
Reset by
Execution of
Illegal
Instruction
Reading
from RESF
Reset by
WDT
Reset by clock
monitor
Reset by illegal-
memory access
Reset
by LVD
RESF TRAP Cleared (0) Cleared (0) Set (1) Cleared
(0)
Held Held Held Held
WDCLRF Held Set (1) Set (1) Held Held
IAWRF Held Held Held Set (1) Held
LVIRF Held Held Held Held Set
(1)
POCRES POCRES0 Held Cleared (0) Held Held Held Held Held Held
CLKRF Cleared (0) Cleared (0) Held Held Held Set (1) Held Held
LVIM LVISEN Cleared (0) Cleared (0) Cleared (0) Held Cleared (0) Cleared (0) Cleared (0) Held
LVIOMSK Held Held Held Held Held Held Held Held
LVIF Held Held Held Held Held Held Held Held
LVIS Cleared
(00H/01H/81H)
Cleared
(00H/01H/81H)
Cleared
(00H/01H/81H)
Held Cleared
(00H/01H/81H)
Cleared
(00H/01H/81H)
Cleared
(00H/01H/81H)
Held
Caution The generation of reset signal other than an LVD reset sets as follows.
• When option byte LVIMDS1, LVIMDS0 = 1, 0: 00H
• When option byte LVIMDS1, LVIMDS0 = 1, 1: 81H
• When option byte LVIMDS1, LVIMDS0 = 0, 1: 01H
Remark The special function register (SFR) mounted depends on the product. See 3.1.4 Special function register (SFR)
area and 3.1.5 Extended special function register (2nd SFR: 2nd Special Function Register) area.

Renesas RL78 Series Specifications

General

Brand	Renesas
Model	RL78 Series
Category	Computer Hardware
Language	English