Index-10
9.4.6 Example of watch error correction of real-time clock ...................................................................... 683
CHAPTER 10 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER ............................................... 686
10.1 Functions of Clock Output/Buzzer Output Controller .......................................................... 686
10.2 Configuration of Clock Output/Buzzer Output Controller .................................................... 688
10.3 Registers Controlling Clock Output/Buzzer Output Controller ........................................... 688
10.3.1 Clock output select register 0 (CKS0) .......................................................................................... 688
10.3.2 Clock Select Register (CKSEL) .................................................................................................... 690
10.3.3 Port mode register 14 (PM14) ...................................................................................................... 691
10.4 Operations of Clock Output/Buzzer Output Controller ........................................................ 692
10.4.1 Operation as output pin ................................................................................................................ 692
10.5 Notes on Clock Output/Buzzer Output Controller ................................................................ 692
CHAPTER 11 WATCHDOG TIMER ..................................................................................................... 693
11.1 Functions of Watchdog Timer ................................................................................................. 693
11.2 Configuration of Watchdog Timer .......................................................................................... 694
11.3 Register Controlling Watchdog Timer .................................................................................... 695
11.3.1 Watchdog timer enable register (WDTE) ...................................................................................... 695
11.4 Operation of Watchdog Timer ................................................................................................. 696
11.4.1 Controlling operation of watchdog timer ....................................................................................... 696
11.4.2 Setting overflow time of watchdog timer ....................................................................................... 697
11.4.3 Setting window open period of watchdog timer ............................................................................ 698
11.4.4 Setting watchdog timer interval interrupt ...................................................................................... 699
CHAPTER 12 A/D CONVERTER ......................................................................................................... 700
12.1 Function of A/D Converter ....................................................................................................... 701
12.2 Configuration of A/D Converter .............................................................................................. 703
12.3 Registers Used in A/D Converter ............................................................................................ 705
12.3.1 Peripheral enable register 0 (PER0) ............................................................................................. 706
12.3.2 A/D converter mode register 0 (ADM0) ........................................................................................ 707
12.3.3 A/D converter mode register 1 (ADM1) ........................................................................................ 716
12.3.4 A/D converter mode register 2 (ADM2) ........................................................................................ 717
12.3.5 10-bit A/D conversion result register (ADCR) ............................................................................... 720
12.3.6 8-bit A/D conversion result register (ADCRH) .............................................................................. 721
12.3.7 Analog input channel specification register (ADS) ........................................................................ 722
12.3.8 Conversion result comparison upper limit setting register (ADUL) ............................................... 725
12.3.9 Conversion result comparison lower limit setting register (ADLL) ................................................ 725
12.3.10 A/D test register (ADTES) .......................................................................................................... 726
12.3.11 A/D port configuration register (ADPC)....................................................................................... 727
12.3.12 A/D converter trigger select register 0 (ADTRGS0) (RL78/F13 only) ......................................... 728
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