Renesas RL78 Series - Page 1745

RL78/F13, F14 CHAPTER 34 ELECTRICAL SPECIFICATIONS (GRADE L)
R01UH0368EJ0210 Rev.2.10 1713
Dec 10, 2015
CSI mode serial transfer timing (master mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1)
CSI mode serial transfer timing (master mode) (during communication at different potential)
(When DAPmn= 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0)
SIp
SOp
t
KCY1
t KL1
t KH1
t SIK1
t KSI1
Input data
t KSO1
Output data
SCKp
SIp
SOp
t
KCY1
tKL1
tKH1
tSIK1
tKSI1
Input data
t
KSO1
Output data
SCKp