Renesas RL78 Series User Manual

RL78/F13, F14 CHAPTER 35 ELECTRICAL SPECIFICATIONS (GRADE K)
R01UH0368EJ0210 Rev.2.10 1755
Dec 10, 2015
(5) During communication at same potential (CSI mode) (slave mode, SCKp … external clock input, special slew
rate)
(TA = -40 to +125C, 4.0 V  EVDD0 = EVDD1 = VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
SCKp cycle time tKCY2 20 MHz  fMCK 10/fMCK ns
10 MHz  fMCK  20 MHz 8/fMCK ns
fMCK  10 MHz 6/fMCK ns
SCKp high-level width, low-level
width
tKH2,
tKL2
tKCY2/2 ns
SIp setup time
(to SCKp)
Note1
tSIK2 1/fMCK + 50 ns
SIp hold time
(from SCKp)
Note 2
tKSI2 1/fMCK + 50 ns
Delay time from SCKp to SOp
output
Note 3
t
KSO2 C = 30 pF
Note 4
2/fMCK + 80 ns
SSIp setup time tSSIK DAP = 0 120 ns
DAP = 1 1/fMCK + 120 ns
SSIp hold time tKSSI DAP = 0 1/fMCK + 120 ns
DAP = 1 120 ns
Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The Slp setup time becomes "to
SCKp" when DAPmn = 0 and CKPmn = 1 or DAPmn = 1 and CKPmn = 0.
2. When DAPmn = 0 and CKPmn = 0 or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes "from
SCKp" when DAPmn = 0 and CKPmn = 1 or DAPmn = 1 and CKPmn = 0.
3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes
“from SCKp” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
4. C is the load capacitance of the SCKp and SOp output lines.
Caution Select the normal input buffer for the SIp, SCKp and SSIp pins and normal output mode and special
slew rate for the SOp pin.
Remarks 1. p: CSIp (p = 00, 01, 10, 11), m: Unit m (m = 0, 1), n: Channel n (n = 0, 1)
2. f
MCK: Serial array unit operation clock frequency

Renesas RL78 Series Specifications

General

Core	RL78
CPU Clock Speed	Up to 32 MHz
Flash Memory	Up to 512 KB
RAM	Up to 32 KB
Operating Voltage	1.6 V to 5.5 V
Low Power Modes	HALT, STOP, SNOOZE
CPU Architecture	16-bit
Temperature Range	-40°C to +85°C
Package	LQFP
Timers	16-bit timers
Communication Interfaces	UART, I2C, LIN
A/D Converter	12-bit