Renesas RL78 Series User Manual

RL78/F13, F14 CHAPTER 35 ELECTRICAL SPECIFICATIONS (GRADE K)
R01UH0368EJ0210 Rev.2.10 1759
Dec 10, 2015
(7) During communication at same potential (simplified I
2
C mode) (SDAr and SCLr: N-ch open-drain output
(EV
DD0 tolerance) mode)
(TA = -40 to +125C, 2.7 V  EVDD0 = EVDD1 = VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter Symbol Conditions MIN. MAX. Unit
SCLr clock frequency fSCL 400
Note
kHz
Hold time when SCLr = ”L” tLOW 4.0 V  VDD  5.5 V,
C
b = 100 pF, Rb = 1.7 k
1300 ns
2.7 V  VDD  4.0 V,
C
b = 100 pF, Rb = 2.7 k
Hold time when SCLr = ”H” tHIGH 4.0 V  VDD  5.5 V,
C
b = 100 pF, Rb = 1.7 k
600 ns
2.7 V  VDD  4.0 V,
C
b = 100 pF, Rb = 2.7 k
Data setup time (reception) tSU : DAT 4.0 V  VDD  5.5 V,
C
b = 100 pF, Rb = 1.7 k
1/f
MCK + 120 ns
2.7 V  VDD  4.0 V,
C
b = 100 pF, Rb = 2.7 k
1/f
MCK + 270 ns
Data hold time (transmission) tHD : DAT 4.0 V  VDD  5.5 V,
C
b = 100 pF, Rb = 1.7 k
0 300 ns
2.7 V  VDD  4.0 V,
C
b = 100 pF, Rb = 2.7 k
Note fCLK  fMCK/4 must also be satisfied.
Simplified I
2
C mode connection diagram (during communication at same potential)
Caution Select the normal input buffer and N-ch open-drain output mode for the SDAr pin and SCLr pin.
Remarks 1. R
b [Ω]: Communication line (SDAr, SCLr) pull-up resistance, Cb [F]: Communication line (SDAr, SCLr) load
capacitance, Vb[V]: Communication line voltage
2. r: IICr (r = 00, 01, 10, 11)
3. f
MCK: Serial array unit operation clock frequency
SDAr
SCLr
SDA
SCL
User's device
Vb
Rb
Vb
Rb
RL78
microcontroller
<R>
<R>
<R>
<R>

Renesas RL78 Series Specifications

General

Core	RL78
CPU Clock Speed	Up to 32 MHz
Flash Memory	Up to 512 KB
RAM	Up to 32 KB
Operating Voltage	1.6 V to 5.5 V
Low Power Modes	HALT, STOP, SNOOZE
CPU Architecture	16-bit
Temperature Range	-40°C to +85°C
Package	LQFP
Timers	16-bit timers
Communication Interfaces	UART, I2C, LIN
A/D Converter	12-bit