Renesas RL78 Series - Page 18

Index-12
13.4 Operations of D/A Converter ................................................................................................... 773
13.4.1 Operation in Normal Mode ........................................................................................................... 773
13.4.2 Operation in Real-Time Output Mode ........................................................................................... 774
13.5 Cautions for D/A Converter ..................................................................................................... 775
CHAPTER 14 COMPARATOR (RL78/F14 Only) ................................................................................. 776
14.1 Overview .................................................................................................................................... 776
14.2 Registers to Control the Comparator ..................................................................................... 778
14.2.1 Peripheral Enable Register 1 (PER1) ........................................................................................... 778
14.2.2 Comparator Control Register (CMPCTL) ...................................................................................... 779
14.2.3 Comparator I/O Select Register (CMPSEL) ................................................................................. 781
14.2.4 Comparator Output Monitor Register (CMPMON) ........................................................................ 782
14.2.5 A/D port configuration register (ADPC) ........................................................................................ 783
14.2.6 D/A converter mode register 2 (DAM2) ........................................................................................ 784
14.2.7 Port mode register 4 (PM4) .......................................................................................................... 785
14.2.8 Port mode register (PM8) ............................................................................................................. 786
14.3 Operation ................................................................................................................................... 787
14.3.1 Noise Filter ................................................................................................................................... 788
14.3.2 Comparator Interrupts .................................................................................................................. 789
14.3.3 Comparator ELC Event Output ..................................................................................................... 789
14.3.4 Comparator Pin Output ................................................................................................................ 789
14.3.5 Stopping or Supplying Comparator Clock ..................................................................................... 789
14.3.6 Comparator Setting Flowchart ...................................................................................................... 790
CHAPTER 15 SERIAL ARRAY UNIT .................................................................................................. 792
15.1 Functions of Serial Array Unit ................................................................................................. 793
15.1.1 3-wire serial I/O (CSI00, CSI01, CSI10, CSI11) ........................................................................... 793
15.1.2 UART (UART0, UART1) ............................................................................................................... 794
15.1.3 Simplified I
2
C (IIC00, IIC01, IIC10, IIC11) .................................................................................... 795
15.2 Configuration of Serial Array Unit .......................................................................................... 796
15.3 Registers Controlling Serial Array Unit .................................................................................. 802
15.3.1 Peripheral enable register 0 (PER0) ............................................................................................. 803
15.3.2 Serial clock select register m (SPSm) .......................................................................................... 804
15.3.3 Serial mode register mn (SMRmn) ............................................................................................... 805
15.3.4 Serial communication operation setting register mn (SCRmn) ..................................................... 807
15.3.5 Higher 7 bits of the serial data register mn (SDRmn) ................................................................... 810
15.3.6 Serial flag clear trigger register mn (SIRmn) ................................................................................ 812
15.3.7 Serial status register mn (SSRmn) ............................................................................................... 813
15.3.8 Serial channel start register m (SSm) ........................................................................................... 815
15.3.9 Serial channel stop register m (STm) ........................................................................................... 816
15.3.10 Serial channel enable status register m (SEm) .......................................................................... 817